As random logic circuitry for microprocessors become more complicated, so does the testing for defects of the circuitry's gates. FIG. 1 is a conceptual block diagram representing the structure of a conventional random logic circuitry. The conventional structure 100 comprises a lattice of logic gates, also called nodes, a sparse matrix. The dots in FIG. 1 represent gates while the lines represent connections between the gates. By analogy to RAM, certain gates could be connected through transfer gates to both a bit line 110 with a row address and a word line 120 with a column address. Assume that gate 140 resides at an intersection of a bit line 110 and a word line 120. This gate 140 can be accessed through its column address and row address. Conventionally, the column and row addresses are each n-bit (n=10 for 1 million gates). Only gates at intersections of bit and word lines can be specifically accessed through row address decoders 150 and column address decoders 160 which decode the row and column addresses, respectively. This conventional architecture of random logic circuitry 100 is well known in the art and will not be further described here.
This architecture presents a problem when testing the random logic circuitry for defective gates. Tests are performed using test codes, which use vectors designed to exercise certain gates. Using this test code, test data are loaded into a data array, and a test calculation or function is performed. The testing of the gates residing at the intersections is simple since gate status may be specifically accessed, and whether the status is correct can be quickly determined. However, with gates not at the intersection of bit and word lines, the status cannot be directly ascertained, so in order to determine if a defect existed, the actual result of the calculation or function must be compared with the correct result. If the actual result does not match the correct result, then one or more of the gates exercised is defective. Then, in conjunction with other tests, the defective gates hopefully can be isolated. If so, and redundant gates exist and are accessible, then these defective gates can be avoided in future calculations and functions. Ideally, the test code would exercise every gate in the random logic circuitry 100, however, this ideal is difficult if not impossible to attain due to the large number of gates and the complexity of the structure. Even with the most skilled code writer(s) and tens of millions of test vectors, perhaps 50%-90% coverage of the gates is typically achieved. This type of testing is very costly since writing test code takes considerable time.
Another way to test the random logic gates is to use a shift register. In this method, transfer gates are placed at each internal node of which one wishes to know the status. These transfer gates are strung together and connected to the shift register. A test data array is loaded, and a test calculation or function is performed. The shift register is then clocked to draw out the status of the nodes with the transfer gates. Each clock cycle draws one bit, or the status of one node. The status of the shift register is then compared with what the status of the nodes should be, thus defective gates can be found. With this method, each gate may be tested if a transfer gate is placed at every node. However, the disadvantage of using shift registers is the time required to draw out the status of the nodes. Because the size of conventional random logic circuitry is very large, the shift registers must also be very large. Thus, many clock pulses are required to draw out the status of all of the nodes, making this method time costly as well.
Accordingly, there exists a need for a method for accessing random logic gates which allows for the testing of more logic gates than conventional methods and which is also faster than conventional methods. The present invention addresses such a need.